Recently, various devices controlled by computers and microprocessors have been replaced by high density nonvolatile semiconductor memory devices. Particularly, in the case of portable computers or notebook size computer systems using battery power, a hard disk device with rotatable magnetic disk used as an auxiliary memory device typically occupies relatively large space. Thus, designers of such systems have become interested in developing electrically erasable and programmable nonvolatile semiconductor memory devices with high density and high performance.
FIG. 1 is a plan view showing a nonvolatile semiconductor memory device containing EEPROM memory cells therein, according to the prior art. Referring to FIG. 1, N type buried diffusion layers 1 used as source/drain regions are extended in a vertical direction under a thick oxide layer, and control gates 2 constituting word lines are extended in a horizontal direction. Under the control gates 2, floating gates 3 cover a portion of the channel regions and a partial portion of the thick oxide layer over the N type buried diffusion layers 1. In this construction, however, as the length of the N type buried diffusion layers 1 increase, their resistance also increases, thus lowering the read and program speed of the cells. In addition, with the increase in capacitance between the bit line and the substrate, the charging speed of the bit lines is lowered and the reading speed is deteriorated.
FIG. 2 is a plan view showing another nonvolatile semiconductor memory device according to the prior art. Here, in order to reduce the diffusion layer resistance, contact holes 4 are formed as shown in FIG. 2, thereby minimizing the extension length of the N type buried diffusion layers 1. That is, by connecting the N type buried diffusion layers 1 to the contact holes 4 via metal wires 5, the resistance can be reduced. However, this construction raises another problem because the formation of the contact holes 4 increases the horizontal size of the memory cell array. Thus, even if the minimum length 6 between adjacent contact holes, the minimum length 7 between one contact hole and an active region and the minimum length 8 between adjacent active regions is achieved, an increase in the horizontal size of the memory cell array is inevitable.
Although the use of contact holes may reduce the resistance to some degree, it typically causes an increase in the capacitance between the substrate and the bit lines. FIG. 3 is an equivalent circuit diagram of the device of FIG. 1. The operation of the cells will now be explained with reference to FIG. 3 and the following TABLE 1.
TABLE 1 ______________________________________ selected unselected B/L B/L B/L W/L W/L K - 1 K K + 1 Substrate ______________________________________ selected program Vpp 0 V 0 V Vd F 0 V cell erase -Vg 0 V 0 V Vcc 0 V 0 V read Vcc 0 V 0 V Vd F 0 V ______________________________________
Referring to FIG. 3 and TABLE 1, in the event cell A is selected for programming, approximately 6-7 Volts is applied to the bit line B/L K, 12 Volts is applied to the selected word line W/L 3 and 0 Volts is applied to the bit line B/L K-1. The application of these potentials causes an injection of hot electrons into the floating gate as will be understood by those skilled in the art. At this point, a ground voltage is also applied to the unselected word lines and the other bit lines B/L K+1 are allowed to float ("F"). Unfortunately, the application of 6-7 Volts to the bit line B/L K and 0 Volts to the unselected word lines (i.e., control gates) may cause drain interference where charge stored on the floating gates of unselected cells is removed through Fowler-Nordheim tunnelling. If the number of cells connected to the bit line B/L is N, the drain interference frequency corresponds to N-1.
As illustrated by TABLE 1, an erase operation is performed by removing the electrons stored on the floating gate 3 through Fowler-Nordheim tunneling. This is achieved by applying a negative voltage -Vg to the selected word line W/L 3 and a power supply voltage VCC to the selected bit line B/L K. A read operation is also performed by applying 1.5 volts (Vd) to the bit line B/L K, the power supply voltage VCC to the selected word line W/L 3 and the ground voltage to the unselected word lines.
FIG. 4 is a cross sectional view taken along line X--X' in FIG. 2. Referring to FIG. 4, under the thick oxide layer 9, N type buried diffusion layers 1 constituting the source/drain regions of the cells are separated from one another by respective channel regions which extend to the face of the substrate. A floating gate 3 separated from a channel region by the gate oxide layer 15 covers a partial portion of the channel region and a partial portion of the thick oxide layer 9 over the N type buried diffusion layer 1. A control gate 2 covers the floating gate 3 and the portion of the channel region that the floating gate 3 does not cover.
FIGS. 5A to 5E show a conventional process of manufacturing the device of FIG. 4. Referring to FIG. 5A, a pad oxide layer 15a and a silicon nitride layer 11 are sequentially deposited over the substrate 100 and then patterned to define openings therein. Thereafter, arsenic ions are implanted into the openings to form the N type buried diffusion layer 1. Then, a plurality of thick oxide layers 9 are formed by thermally oxidizing the openings at 900.degree. C. for over 10 hours.
Referring to FIG. 5B, after removing the silicon nitride layer 11 and the pad oxide layer 15a, a tunnel oxide layer 10 is grown. Thereafter, the polysilicon to be used as the floating gate 3 is deposited over the tunnel oxide layer 10. Openings are then formed by patterning the layer of polysilicon and the tunnel oxide layer 10 via a typical photo etching process using the photosensitive film 12 as an etching mask. This patterning step defines a first polysilicon pattern 3a. When forming the tunnel oxide layer 10, due to the lateral diffusion of the ions implanted to form the N type buried diffusion layer 1, the oxide layer over the channel region adjacent to the N type buried diffusion layer 1 becomes thicker than that over the channel region which is not affected by the lateral diffusion of the implanted ions. In addition, with an increase in the ion density to decrease the resistance of the drain region, the thickness difference in the oxide layer becomes greater, causing uneven device characteristics. That is, during the memory cell's program mode of operation, the uneven thickness of the tunnelling oxide layer causes an unevenness in the threshold voltage of the cell. This problem also exists during the erase operation. In particular, when erasing using Fowler-Nordheim current from the floating gate to the source or drain, the unevenness in the cell's electrical characteristic becomes much greater.
Referring now to FIG. 5C, an interlayer insulating film 13 is formed over the first polysilicon pattern 3a and over the portion of the channel region that the first polysilicon pattern 3a does not cover, by a thermal oxidation process. Thereafter, a second layer of polysilicon for the control gate 2 is deposited thereon, and then the second layer of polysilicon, the interlayer insulating film 13 and the first polysilicon pattern 3a are etched via the photoetching process to form the control gate 2 and the floating gates 3. Problems associated with this etching process will now be discussed with reference to FIGS. 5D and 5E.
FIG. 5D is a cross sectional view taken along line Z--Z' in FIG. 2. FIG. SE is a cross sectional view taken along line Y--Y' in FIG. 2. In etching the second layer of polysilicon 2, the interlayer insulating film 13 and the first polysilicon pattern 3a via the photo etching process, the substrate 100 is not exposed. However, when etching the interlayer insulating film 13 after etching the second layer of polysilicon in the construction of FIG. 5E, there occurs a problem that the oxide layer is also etched, thus exposing the surface of the substrate 100. The exposed substrate is damaged during the etching process for forming the floating gate, making it impossible to obtain a normal contact characteristic.
Thus, notwithstanding the above described methods of forming nonvolatile memory devices containing EEPROM memory cells, there continues to be a need for methods of forming memory devices having improved electrical characteristics and memory devices formed thereby.